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ATmega128
? Bits 11..0 – EEAR11..0: EEPROM Address
The EEPROM Address Registers – EEARH and EEARL – specify the EEPROM address in the 4
Kbytes EEPROM space. The EEPROM data bytes are addressed linearly between 0 and 4096.
The initial value of EEAR is undefined. A proper value must be written before the EEPROM may
be accessed.
EEPROM Data
Register – EEDR
Bit
7
6
5
4
3
2
1
0
MSB
LSB
EEDR
Read/ W rite
Initial Value
R/ W
0
R/ W
0
R/ W
0
R/ W
0
R/ W
0
R/ W
0
R/ W
0
R/ W
0
? Bits 7..0 – EEDR7.0: EEPROM Data
For the EEPROM write operation, the EEDR Register contains the data to be written to the
EEPROM in the address given by the EEAR Register. For the EEPROM read operation, the
EEDR contains the data read out from the EEPROM at the address given by EEAR.
EEPROM Control
Register – EECR
Bit
Read/ W rite
Initial Value
7
–
R
0
6
–
R
0
5
–
R
0
4
–
R
0
3
EERIE
R/ W
0
2
EEMWE
R/ W
0
1
EEWE
R/ W
X
0
EERE
R/ W
0
EECR
? Bits 7..4 – Res: Reserved Bits
These bits are reserved bits in the ATmega128 and will always read as zero.
? Bit 3 – EERIE: EEPROM Ready Interrupt Enable
W riting EERIE to one enables the EEPROM Ready Interrupt if the I-bit in SREG is set. W riting
EERIE to zero disables the interrupt. The EEPROM Ready interrupt generates a constant inter-
rupt when EE W E is cleared.
? Bit 2 – EEMWE: EEPROM Master Write Enable
The EEM W E bit determines whether setting EE W E to one causes the EEPROM to be written.
W hen EEM W E is written to one, writing EE W E to one within four clock cycles will write data to
the EEPROM at the selected address. If EEM W E is zero, writing EE W E to one will have no
effect. W hen EEM W E has been written to one by software, hardware clears the bit to zero after
four clock cycles. See the description of the EE W E bit for an EEPROM write procedure.
? Bit 1 – EEWE: EEPROM Write Enable
The EEPROM W rite Enable Signal EE W E is the write strobe to the EEPROM. W hen address
and data are correctly set up, the EE W E bit must be set to write the value into the EEPROM.
The EEM W E bit must be set when the logical one is written to EE W E, otherwise no EEPROM
write takes place. The following procedure should be followed when writing the EEPROM (the
order of steps 3 and 4 is not essential):
1. W ait until EE W E becomes zero.
2. W ait until SPMEN in SPMCSR becomes zero.
3. W rite new EEPROM address to EEAR (optional).
4. W rite new EEPROM data to EEDR (optional).
5. W rite a logical one to the EEM W E bit while writing a zero to EE W E in EECR.
6. W ithin four clock cycles after setting EEM W E, write a logical one to EE W E.
21
2467X–AVR–06/11
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